1. Field of the Invention
The present invention relates to a 3-way Doherty power amplifier using a driving amplifier, and more particularly, to a 3-way Doherty power amplifier using a driving amplifier in which driving amplifiers are connected to the front stages of a carrier amplifier and a peaking amplifier, respectively, which constitute the Doherty power amplifier, so as to obtain a high gain and a high efficiency.
2. Description of the Related Art
Doherty power amplifiers exhibit a high efficiency at a relatively low output power, so that Doherty power amplifiers are being widely researched even now. However, modulation signals used in a recent communication system have a high peak-to-average power ratio (PAPR) of 9 dB or higher while general Doherty power amplifiers are limited to having a high efficiency at 6 dB back-off power (BOP), so that, in order to compensate therefor, Doherty power amplifiers with a more expanded concept have been proposed. As methods for providing a high efficiency at a higher BOP, N-way and asymmetric Doherty power amplifiers have been developed. However, these Doherty power amplifiers also have a disadvantage in that, after a high efficiency is generated in a BOP domain, gain and efficiency are reduced, and thus the maximum output power is generated.
FIG. 1 is a circuit diagram illustrating the configuration of a conventional 3-way Doherty power amplifier 100.
Referring to FIG. 1, an input signal is divided into signals having the same amplitude and into the respective transmission lines by a power distributor 101. The divided signals have a phase difference of 90 degrees by a λ/4 transmission line 102, which is disposed at the front ends of the input units of peaking amplifiers 105 and 106, and then are inputted to the first peaking 105 and second peaking amplifier 106, respectively. An input matching circuit 103 includes a first matching circuit, a second matching circuit, and a third matching circuit, which are located at the respective transmission lines and match the input impedances of amplifiers 104, 105, and 106, respectively. An output matching circuit 107 includes a fourth matching circuit, a fifth matching circuit, and a sixth matching circuit, which maximize the gains and efficiencies of the amplifier 104, 105, and 106, respectively.
When input power is in an input range lower than a preset value, the first peaking amplifier 105 and second peaking amplifier 106 do not operate, and only the carrier amplifier 104 operates. The preset value is predetermined by circuit designers.
In a low input range in which only the carrier amplifier 104 operates, the load impedance at the output terminal of the carrier amplifier 104 increases by a λ/4 transmission line 111.
In this case, in order to prevent the output of the carrier amplifier 104 from leaking to the first peaking amplifier 105 and second peaking amplifier 106, 50Ω transmission lines 109 and 110 are added to the output terminals of the first peaking amplifier 105 and second peaking amplifier 106, respectively. This allows an impedance viewed to the first peaking amplifier 105 and second peaking amplifier 106 from the output of the carrier amplifier 104 to have a high value.
In order to compensate for a signal delay by the 50Ω transmission lines 109 and 110 added to the respective peaking amplifiers, a 50Ω transmission line 108 is additionally connected to the output terminal of the carrier amplifier 104.
In addition, in order to achieve an impedance matching between the characteristic impedance of the 3-way Doherty amplifier and the output impedance of the carrier amplifier 104, the first peaking amplifier 105, and the second peaking amplifier 106, an output impedance transformation transmission line 112 is connected to the output.
When a power inputted to the 3-way Doherty power amplifier 100 becomes higher than a preset value, the carrier amplifier 104, the first peaking amplifier 105, and the second peaking amplifier 106 come to operate at the same time. Generally, an N-way Doherty power amplifier uses an N-way power distributor at the input stage thereof, and thus has the features that the gain of the carrier amplifier becomes low, and that the gain and efficiency thereof decrease until arriving at a saturation output power after a high efficiency is exhibited at a BOP.
FIG. 2 is a circuit diagram illustrating the configuration of a conventional inverse class-E power amplifier 200.
Referring to FIG. 2, the input impedance of a power amplifier 203 is matched by an input matching circuit 201. The output impedance of a power amplifier 203 is matched by an output matching circuit 207. The second harmonic component of a signal inputted to the power amplifier 203 is minimized by a second harmonic adjustment line 202, all harmonic impedances becomes relatively lower than an input impedance by an output harmonic adjustment line 206, so that a high efficiency is obtained.
However, the aforementioned conventional 3-way Doherty power amplifier 203 has a characteristic of a high efficiency at a high BOP, but has a disadvantage in that the efficiency and gain decrease until a high efficiency is again exhibited in a maximum output range after the high efficiency has been exhibited in at a low output range. In addition, the soft turn-on phenomenon, which is the non-linear characteristic of elements, prevents the peaking amplifier from generating the maximum output power, thereby reducing the efficiency.